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features ? also known as smcs332spw ? 3 identical bidirectional spacewire links allowing ? full duplex communication ? transmit rate from 1.25 up to 200 mbit/s in each d irection ? derived from the tss901e-smcs332 triple ieee 1355 h igh speed controller ? known anomalies of the tss901e chip corrected ? slightly different startup behavior ? communication memory interface (comi) ? autonomous accesses to a communication memory ? host control interface (hoci) ? gives read/write accesses to the at7911e configura tion registers ? gives read/write accesses to the spacewire channel s ? arbitration unit ? allows two at7911e to share one dual port ram with out external arbitration ? scalable databus width ? 8/16/32 bit width available ? allows flexible integration with any cpu type ? allows little endian and big endian configuration ? performance ? at 3.3v: 100 mbit/s full duplex communication in e ach direction ? at 5v: 200 mbit/s full duplex communication in eac h direction ? operating range ? voltages ? 3v to 3.6v ? 4.5v to 5.5v ? temperature ? - 55c to +125c ? maximum power consumption ? at 3.6v with a 15mhz clock : 0.4 w ? at 5.5v with a 25 mhz clock : 1.7 w ? radiation performance ? total dose tested successfully up to 50 krad (si) ? no single event latchup below a let of 80 mev/mg/c m2 ? esd better than 2000v ? quality grades : ? qml-q or v with smd ? package : 196 pins mqfpl ? mass : 12grams triple spacewire links high speed controller at7911e
2 7737b?aero?05/08 at7911e 1. description the at7911e provides an interface between three spa cewire links according to the spacewire standard ecss-e-50-12a specification and a data pro cessing node consisting of a control pro- cessing unit and a communication data memory. the at7911e was designed by eads astrium in germany under the name 'smcs332spw" for "scalable multi-channel communication subsystem for spacewire". it is manufactured using the seu hardened cell library from atmel mg2rt cmo s 0.5m radiation tolerant sea of gates technology. for any technical question relative to the function ality of the at7911e please contact atmel technical support at assp-applab.hotline@nto.atmel.com . this document shall be read in conjunction with eads astrium 'smcs332spw user manual' . the complete user manual of the at7911e also called smcs332spw is available at www.atmel.com . the at7911e provides hardware supported execution o f the major parts of the interprocessor communication protocol, particularly: ? transfer of data between two nodes of a multi-proc essor system with minimal host cpu intervention ? execution of simple commands to provide basic feat ures for system control functions ? provision of fault tolerant features. target applications are heterogeneous multi-process or systems supported by scalable inter- faces including the little/big endian byte swapping . the at7911e connects modules with different processors (e.g. tsc695f, at697e and othe rs). any kind of network topology could be realized through the high speed point-to-point spac ewire links (see the section ?applications?). it can also be used for modules without any communi cation features such as special image com- pression chips, some signal processors, application specific programmable logic or mass memory. the at7911e may also be used in single board system s where standardised high speed inter- faces are needed and systems containing "non-intell igent" modules such as a/d-converter or sensor interfaces which can be assembled with the a t7911e thanks to the "control by link" feature.
3 7737b?aero?05/08 at7911e figure 1. at7911e block diagram the at7911e is supported by vspworks from wind rive r, a commercially available distributed real-time kernel. it is a multi-tasking as well as a multi-processor operating system. the main goals are to enable programming at a higher level t o configure and to perform communication and to administer the tasks on a board with multipl e processes running in parallel. the vspworks kernel supports multiple processors an d application specific chips, e.g. the tsc21020, the sparc tsc695f, the at697 etc.... thus it is possible to run a heterogeneous multiprocessor system with a single operating syste m without consideration of the hardware platform. spacewire receive transmit protocol channel1 channel2 channel3 comi hoci prci jtag d/s rcv 1 d/s trm 1 d/s rcv 2 d/s trm 2 d/s trm 3 d/s rcv 3 cmadr cm_control cmdata hadr h_control hdata hintr cpur ses test clock reset
4 7737b?aero?05/08 at7911e 2. pin configuration table 1. pin assignment pin number name pin number name pin number name pin number name pin number name 1 pllout 41 vcc 81 hdata28 121 cmdata0 161 gnd 2 gnd 42 gnd 82 hdata29 122 cmdata1 162 cmdata27 3 vcc 43 hdata0 83 vcc 123 cmdata2 163 cmdata28 4 clk 44 hdata1 84 gnd 124 vcc 164 cmdata29 5 reset* 45 hdata2 85 hdata30 125 gnd 165 cmdata30 6 clk10 46 hdata3 86 hdata31 126 cmdata3 166 cmdata31 7 hostbige 47 hdata4 87 cpur* 127 cmdata4 167 gnd 8 tck 48 hdata5 88 ses0* 128 cmdata5 168 gnd 9 tms 49 hdata6 89 ses1* 129 vcc 169 vcc_3volt 10 tdi 50 vcc 90 ses2* 130 gnd 170 gnd 11 trst* 51 gnd 91 ses3* 131 cmdata6 171 gnd 12 tdo 52 hdata7 92 cam 132 cmdata7 172 vcc 13 vcc 53 hdata8 93 coci 133 cmdata8 173 gnd 14 gnd 54 hdata9 94 coco 134 vcc 174 gnd 15 hsel* 55 hdata10 95 cmcs0* 135 gnd 175 nc 16 hrd* 56 hdata11 96 cmcs1* 136 cmdata9 176 ldi1 17 hwr* 57 vcc 97 vcc 137 cmdata10 177 lsi1 18 hack 58 gnd 98 gnd 138 cmdata11 178 ldo1 19 hintr* 59 hdata12 99 cmrd* 139 cmdata12 179 lso1 20 vcc 60 hdata13 100 cmwr* 140 cmdata13 180 ldi2 21 gnd 61 hdata14 101 cmadr0 141 cmdata14 181 lsi2 22 hadr0 62 hdata15 102 cmadr1 142 vcc 182 nc 23 hadr1 63 hdata16 103 cmadr2 143 gnd 183 vcc 24 hadr2 64 hdata17 104 cmadr3 144 cmdata15 184 vcc 25 hadr3 65 vcc 105 cmadr4 145 cmdata16 185 vcc 26 hadr4 66 gnd 106 vcc 146 cmdata17 186 ldo2 27 hadr5 67 hdata18 107 gnd 147 cmdata18 187 lso2 28 hadr6 68 hdata19 108 cmadr5 148 cmdata19 188 ldi3 29 hadr7 69 hdata20 109 cmadr6 149 cmdata20 189 lsi3 30 vcc 70 hdata21 110 cmadr7 150 vcc 190 ldo3 31 gnd 71 hdata22 111 cmadr8 151 gnd 191 lso3 32 bootlink 72 hdata23 112 cmadr9 152 cmdata21 192 time_code_sync 33 scmsadr0 73 vcc 113 cmadr10 153 cmdata22 193 gnd 34 smcsadr1 74 gnd 114 cmadr11 154 cmdata23 194 gnd 35 smcsadr2 75 hdata24 115 vcc 155 vcc 195 vcc 36 smcsadr3 76 hdata25 116 gnd 156 gnd 196 gnd 37 smcsid0 77 hdata26 117 cmadr12 157 cmdata24 38 smcsid1 78 vcc 118 cmadr13 158 cmdata25 39 smcsid2 79 gnd 119 cmadr14 159 cmdata26 40 smcsid3 80 hdata27 120 cmadr15 160 vcc
5 7737b?aero?05/08 at7911e 3. pin description table 2. pin description signal name (1)(3) type (2)(4) function 5v 0.5v max. output current [ma] 3.3v 0.3v max. output current [ma] load [pf] hsel* i select host interface hrd* i host interface read strobe hwr* i host interface write strobe hadr(7:0) i at7911e register address lines. these address lines will be used to access (address) the at7911e registers. hdata(31:0) io/z at7911e data 3 1.5 50 hack o/z host acknowledge. the at7911e deasserts this output to add waitstates to an at7911e access. after at7911e is ready this output will be asserted. 3 1.5 50 hintr* o/z host interrupt request line 3 1.5 50 smcsadr(3:0 ) i address. the binary value of these lines will be co mpared with the value of the id lines. smcsid(3:0) i id lines: offers possibility to use sixteen at7911e within one hsel* hostbige i 0: host i/f little endian 1: host i/f big endian bootlink i 0: control by host 1: control by link cmcs(1:0)* o/z communication memory select lines. these pins are asserted as chip selects for the corresponding bank s of the communication memory. 6 3 25 cmrd* o/z communication memory read strobe. this pin is asser ted when the at7911e reads data from memory. 6 3 25 cmwr* o/z communication memory write strobe. this pin is asse rted when the at7911e writes to data memory. 6 3 25 cmadr(15:0) o/z communication memory address. the at7911e outputs a n address on these pins. 6 3 25 cmdata(31:0) ioz communication memory data. the at7911e inputs and outputs data from and to com. memory on these pins. 3 1.5 25 coci i communication interface 'occupied' input signa l coco o communication interface 'occupied' output sign al 3 1.5 50 cam i communication interface arbitration master input si gnal 1: master 0: slave cpur* o cpu reset signal (can be used as user defined flag) 3 1.5 50 ses(3:0)* o specific external signals (can be used as user defined flags) 3 1.5 50 ldi1 i link data input channel 1 lsi1 i link strobe input channel 1 ldo1 o link data output channel 1 12 6 25
6 7737b?aero?05/08 at7911e notes: 1. groups of pins represent busses where the h ighest number is the msb. 2. o = output; i = input; z = high impedance 3. (*) = active low signal 4. o/z = if using a configuration with two at7911es these signals can directly be connected together (wiror) lso1 o link strobe output channel 1 12 6 25 ldi2 i link data input channel 2 lsi2 i link strobe input channel 2 ldo2 o link data output channel 2 12 6 25 lso2 o link strobe output channel 2 12 6 25 ldi3 i link data input channel 3 lsi3 i link strobe input channel 3 ldo3 o link data output channel 3 12 6 25 lso3 o link strobe output channel 3 12 6 25 trst* i test reset. resets the test state machine. tck i test clock. provides an asynchronous clock for jtag boundary scan. tms i test mode select. used to control the test stat e machine. tdi i test data input. provides serial data for the bound ary scan logic. tdo o test data output. serial scan output of the boundar y scan path. 3 1.5 50 reset* i reset. sets the at7911e to a known state. this inpu t must be asserted (low) at power-up. the minimum width of reset low is 5 cycles of clk10 in parallel with clk running. clk i external clock input to at7911e (max. 25 mhz). must be derived from ram access time. clk10 i external clock input to at7911e ds-links (applicati on specific, nominal 10 mhz). used to generate to tran smission speed and link disconnect timeout. time_code_sy nc i a falling edge on this signal sends (if enabled) th e internal spacewire time code value over the links pllout o output of internal pll. used to connect a network o f external rc devices. this is not a pll clock output . vcc_3volt i pll control signal - configure pll for 3.3v or 5v o peration vcc = 5 volt: connect this signal with gnd vcc = 3.3 volt: connect this signal with vcc vcc power supply gnd ground signal name (1)(3) type (2)(4) function 5v 0.5v max. output current [ma] 3.3v 0.3v max. output current [ma] load [pf]
7 7737b?aero?05/08 at7911e 4. interfaces the at7911e provides an interface between three spa cewire links according to the spacewire standard ecss-e-50-12a specification and a data pro cessing node consisting of a central pro- cessing unit and a communication data memory. the at7911e consists of the following blocks (see f igure 1): ? three bidirectional spacewire channels ? communication memory interface (comi) ? host control interface (hoci) ? protocol command interface (prci) ? jtag test interface 4.1 three bidirectional spacewire channels, three bidirectional spacewire channels, all comprising the ds-link spacewire cell, receive and transmit sections (each including fifos) and a prot ocol processing unit (ppu). each channel allows full duplex communication up to 200 mbit/s i n each direction. with protocol command execution a higher level of communication is suppor ted. link disconnect detection and parity check at character level are performed. a checksum generation for a check at packet level can be enabled. the transmit rate is selectable between 1.25 and 20 0 mbit/s. the startup transmit rate is 10 mbit/s. for special applications the data transmit rate can be programmed to values even below 10 mbit/s; the lowest possible spacewire transmit r ate is 1.25 mbit/s (the next values are 2.5 and 5 mbit/s). 4.1.1 ppu functional description since the protocol processing unit (ppu) determines a major part of the at7911e functionality, the principal blocks of the ppu and their function are described here. the ppu unit functionality is provided for each spacewire channel of the at791 1e. 4.1.1.1 protocol execution unit this unit serves as the main controller of the ppu block. it receives the character from the spacewire cell and interprets (in protocol mode) th e four header data characters received after an eop control character. if the address field matc hes the link channel address and the com- mand field contains a valid command then forwarding of data into the receive fifo is enabled. if the command field contains a "simple control comman d" then the execution request is forwarded to the command execution unit. the protocol execution unit also enables forwarding of header data characters to the acknowl- edge generator and provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple control commands". the protocol execution unit is disabled in "transpa rent" or ?wormhole routing? operation mode. 4.1.1.2 receive, transmit, acknowledge the transmit and receive fifos decouple the spacewi re link related operations from the at7911e related operations in all modes and such al lows to keep the speed of the different units even when the source or sink of data is temporarily blocked.
8 7737b?aero?05/08 at7911e in the protocol mode an additional fifo (acknowledg e fifo) is used to decouple sending of acknowledges from receiving new data when the trans mit path is currently occupied by a run- ning packet transmission. 4.1.1.3 command execution unit this unit performs activating resp. deactivating of the cpu reset and the specific external sig- nals and provides the capability to reset one or al l links inside the at7911e, all actions requested by the decoded commands from the protocol execution unit. the unit contains a register controlling the enable /disable state of safety critical commands which is set into the 'enable' state upon command r equest and which is reset after a safety criti- cal command has been executed. the cpu reset and the specific external signals are forwarded to the protocol command inter- face (prci). 4.2 communication memory interface (comi) the comi performs autonomous accesses to the commun ication memory of the module to store data received via the links or to read data to be t ransmitted via the links. the comi consists of individual memory address generators for the receiv e and transmit direction of every spacewire link channel. the access to the memory is controlle d via an arbitration unit providing a fair arbi- tration scheme. two at7911e can share one dpram wit hout external arbitration logic. the data bus width is scalable (8/16/32 bit) to all ow flexible integration with any cpu type. operation in little or big endian mode is configura ble through internal registers. the comi address bus is 16 bit wide allowing direct access of up to 64k words (32 bits) of the dpram. two chip select signals are provided to allo w splitting of the 64k address space in two memory banks. 4.3 host control interface (hoci) the hoci gives read and write access to the at7911e configuration registers and to the spacewire channels for the controlling cpu. viewed from the cpu, the interface behaves like a peripheral that generates acknowledges to synchroni ze the data transfers and which is located somewhere in the cpu's address space. packets can be transmitted or received directly via the hoci. in this case the communication memory (dpram) is not strictly needed. however, in this case the packet size should be limited to avoid frequent cpu interaction. the data bus width is scalable (8/16/32 bit) to all ow flexible integration with any cpu type. the byte alignment can be configured for little or big endian mode through an external pin. additionally, the hoci contains the interrupt signa lling capability of the at7911e by providing an interrupt output, the interrupt status register and interrupt mask register to the local cpu. a special pin is provided to select between control of the at7911e by hoci or by link. if control by link is enabled, the host data bus functions as a 32-bit general purpose interface (gpio). 4.4 protocol command interface (prci) the prci collects the decoded commands from all ppu s and forwards them to external circuitry via 5 special pins.
9 7737b?aero?05/08 at7911e 4.5 jtag test interface it represents the boundary scan testing provisions specified by ieee standard 1149.1 of the joint testing action group (jtag). the at7911e test access port and on-chip circuitry is fully compliant with the ieee 1149.1 specification. the t est access port enables boundary scan test- ing of circuitry connected to the at7911e i/o pins.
10 7737b?aero?05/08 at7911e 5. control interface the at7911e can be configured/controled through two interfaces: ? hoci interface ? link control interface 5.1 hoci interface the host control interface is especialy designed fo r access to internal at6911e registers by a local controller (controller, fpga etc.). the detailed description of this operation mode can be found in the section 5.4 of the 'smcs332spw user manual'. 5.2 link control interface link control is the feature of the at7911e that al lows the control of the at7911e not only via hoci but via one of the three links. this allows to use the at7911e in systems without a local controller. since the hoci is no longer used in thi s operation mode, it is instead available as a set of general purpose i/o (gpio) lines. the detailed description of this operation mode can be found in the section 5.4 of the 'smcs332spw user manual'.
11 7737b?aero?05/08 at7911e 6. operating modes according to the different protocol formats expecte d for the operation of the at7911e, two major operation modes are implemented into the at7911e. f or each link channel the operation modes are chosen individually by setting the respective c onfiguration registers via the hoci or via the link. 6.1 simple interprocessor communication (sic) protoc ol mode this mode executes the simple interprocessor commun ication protocol as described in the chapter 13 of the 'smcs332spw user manual'. the following capabilities of the protocol are impl emented into the at7911e: ? interpretation of the first 4 data characters as t he header bytes of the protocol ? autonomous execution of the simple control command s as described in the above mentioned chapter ? autonomous acknowledgement of received packets if configured in transmit direction no interpretation of the data is performed. this means that for transmit pack- ets, the four header bytes must be generated by the host cpu and must be available as the first data read from the communication memory. eop contro l characters are automatically inserted by the at7911e when one configured transfer from th e communication memory has finished. 6.2 transparent mode (default after reset) this mode allows complete transparent data transfer between two nodes without performing any interpretation of the databytes and without generat ing any acknowledges. it is completely up to the host cpu to interpret the received data and to generate acknowledges if required. the at7911e accepts eop and eep control tokens as p acket delimiters and generates autono- mously eop or no eop (as configured) marker after e ach end of a transmission packet. the transparent mode includes as a special submode: wormhole routing. 6.2.1 wormhole routing this mode allows hardware routing of packets by the at7911e. it is a submode of the transpar- ent mode. the at7911e introduces a wormhole routin g function similar to the routing implemented in the spacewire router. each of the th ree links and the at7911e itself can be assigned an eight bit address. when routing is enab led in the at7911e, the first byte of a packet will be interpreted as the address destination byte , analysed and removed from the packet (header deletion). if this address matches one of t he two other link addresses or the at7911e address assigned previously, the packet will be aut omatically forwarded to this link or the fifo of the at7911e. if the header byte does not match a link address, the packet will be written to the internal fifo as well and an error interrupt (m askable) will be raised. 7. fault tolerance the spacewire standard specifies low level checks a s link disconnect, credit value, sequence and parity at token level. the at7911e provides, th rough the protocol processing unit, features
12 7737b?aero?05/08 at7911e to reset a link or all links inside the at7911e, to reset the local cpu or to send special signals to the cpu commanded via the links. additionally it is possible to enable a checksum co der/decoder to have fault detection capabili- ties at packet level.
13 7737b?aero?05/08 at7911e 8. typical applications the at7911e can be used for single board systems wh ere standardised high speed interfaces are needed. even "non-intelligent" modules such as a/d-converter or sensor interfaces can be assembled with the at7911e because of the "control by link" feature. the complete control of the at7911e can be done via link from a central con troller-node. the at7911e is a very high speed, scalable link-int erface chip with fault tolerance features. the initial exploitation is for use in multi-processor systems where the standardization or the high speed of the links is an important issue and where reliability is a requirement. further application examples are heterogeneous systems or modules witho ut any communication features as spe- cial image compression chips, certain signal proces sors, application specific programmable logic or mass memory. the figure below shows the at7911e (also called smc s332spw) embedded in a typical mod- ule environment: figure 8-1. typical application select a oe a we a data a addr a select b oe b we b data b addr b dual port communication memory bank 0 hostbige bootlink reset clk clk10 spacewire link 1 spacewire link 2 spacewire link 3 4 4 4 5 time_code_sync jtag hintr hsel hrd hwr hack hdata hadr smcsadr smcsid interrupt in chip selects read write wait/ack data address cmcs1 cmrd cmwr cmdata cmadr cmcs0 pllout coci coco cam select a oe a we a data a addr a select b oe b we b data b addr b dual port communication memory bank 1 cpur ses 4 4 8 32 32 16 4 vcc gnd id processor smcs332spw
14 7737b?aero?05/08 at7911e 8.1 at7911e connected with the tss901e (or smcs332) the new ecss-e-50-12a spacewire standard, used by t he at7911e and the ieee-1355 stan- dard used by the old tss901e are compatible, howeve r the tss901e has a slightly different startup behavior, the tss901e must be started first on a link connecting with the at7911e. 8.2 at7911e differences with the tss901e (or smcs332 ) a few differences between the at7911e and the tss90 1e exist in the registers and in the pinout. these differences are detailed in the secti on 14 of the ?smcs332spw user manual?. 8.3 handling empty packets an anomaly due to the spacewire codec implemented i n the at7911e affect the behavior of the at7911e when receiving empty packets. the descripti on of this anomaly and the possible workaround are given in the section 12 of the ?smcs 332spw user manual?.
15 7737b?aero?05/08 at7911e 9. pll filter the at7911e embeds a pll to generate its internal c lock reference. the pllout pin of the pll is the output of the at7911e that allows connec tion of the external filter of the pll. the fol- lowing figure presents the connection of the pll fi lter. figure 9-1. pll filter table 9-1. pll filter recommended components 10. power supply to achieve its fast cycle time, the at7911e is desi gned with high speed drivers on output pins. large peak currents may pass through a circuit boar d?s ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. these transient currents can cause disturbances on the po wer and ground lines. to minimize these effects, the at7911e provides separate supply pins for its internal logic and for its external drivers. all gnd pins should have a low impedance path to gr ound. a ground plane is required in at7911e systems to reduce this impedance, minimizin g noise. the vcc pins should be bypassed to the ground plane using approximately 10 high-frequency capacitors (0.1 f ceramic). keep each capacitor?s l ead and trace length to the pins as short as possible. this low inductive path provides the at79 11e with the peak currents required when its output drivers switch. the capacitors? ground leads should also be short and connect directly to the ground plane. this provides a low impedance ret urn path for the load capacitance of the at7911e output drivers. the following pins must have a capacitor: 20, 78, 1 29, and 155. the remaining capacitors should be distributed equally around the at7911e. vcc = +5v 0.5v vcc = +3.3v 0.3v r1 1,8 k 5%, ?w r1 2,0 k 5%, ?w c1 33pf, 5% c1 33pf, 5% c2 820pf, 5% c2 760pf, 5% at7911e
16 7737b?aero?05/08 at7911e 11. electrical characteristics 11.1 absolute maximum ratings table 11-1. absolute maximum ratings stresses above those listed may cause permanent dam age to the device. parameter symbol value unit supply voltage vcc -0.5 to +7 v i/o voltage -0.5 to vcc + 0.5 v operating temperature range (ambient) ta -55 to +125 c junction temperature tj tj < ta +20 c storage temperature range tstg -65 to +150 c thermal resistance: junction to case rthjc 4 c/w
17 7737b?aero?05/08 at7911e 11.2 dc electrical characteristics the at7911e can work with vcc = + 5 v 0.5 v and v cc = + 3.3v 0.3v. although specified for ttl outputs, all at7911e outputs are cmos compa tible and will drive to vcc and gnd assuming no dc loads. table 11-2. 5v operating range dc characteristics. notes: 1. applicable for hdata[31:0], hack, hintr*, c mdata[31:0], coci, cpur*, ses[3:0]* and tdo pins 2. applicable for cmcs[1:0]*, cmrd*, cmwr* and cmadr [31:0] pins 3. applicable for ldo1, lso1, ldo2, lso2, ldo3 and l so3 pins table 11-3. 3.3v operating range dc characteristics. notes: 1. applicable for hdata[31:0], hack, hintr*, c mdata[31:0], coci, cpur*, ses[3:0]* and tdo pins 2. applicable for cmcs[1:0]*, cmrd*, cmwr* and cmadr [31:0] pins 3. applicable for ldo1, lso1, ldo2, lso2, ldo3 and l so3 pins parameter symbol min. max. unit conditions operating voltage vcc 4.5 5.5 v input high voltage vih 2.2 v input low voltage vil 0.8 v output high voltage voh 2.4 v iol = 3, 6, 12ma / vcc = vcc(min) output low voltage vol 0.4 v ioh = 3, 6, 12ma / vcc = v cc(min) output short circuit current ios 90 (1) 180 (2) 270 (3) ma ma ma vout = vcc vout = gnd parameter symbol min. max. unit conditions operating voltage vcc 3.0 3.6 v input high voltage vih 2.0 v input low voltage vil 0.8 v output high voltage voh 2.4 v iol = 1.5, 3, 6ma / vcc = vcc(min) output low voltage vol 0.4 v ioh = 1, 2, 4ma / vcc = vc c(min) output short circuit current ios 50 (1) 100 (2) 155 (3) ma ma ma vout = vcc vout = gnd
18 7737b?aero?05/08 at7911e 11.3 power consumption max. power consumption figures at vcc = 5.5v; -55c ; clk = 25 mhz are presented in the fol- lowing table. table 11-4. 5v power consumption max. power consumption figures at vcc = 3.6v; -55c ; clk = 15 mhz are presented in the fol- lowing table. table 11-5. 3.3v power consumption operation mode power consumption [ma] not clocked 8 at7911e in reset 75 at7911e in idle (1) 1. idle means clk = 25 mhz, all three links started and running at 10mbit/s, no activity on hoci and comi 115 maximum 310 operation mode power consumption [ma] not clocked 4 at7911e in reset 24 at7911e in idle (1) 1. idle means clk = 15 mhz, all three links started and running at 10mbit/s, no activity on hoci and comi 38 maximum 100
19 7737b?aero?05/08 at7911e 11.4 ac electrical characteristics the following table gives the worst case timings me asured by atmel on the 4.5v to 5.5v operat- ing range table 11-6. 5v operating range timings. the following table gives the worst case timings me asured by atmel on the 3.0v to 3.6v operat- ing range table 11-7. 3.3v operating range timings for guaranteed timings on the two operating voltage ranges, refer to the section 9 of the ?smcs332spw user manual? parameter symbol min. max. unit propagation delay clk low to hack high tp1 29 ns propagation delay clk high to cmcs0* low tp2 18 ns propagation delay clk high to cmadr0 high tp3 17 ns propagation delay clk10 high to ldo1 high tp4 30 ns propagation delay clk10 high to ldo2 high tp5 32 ns propagation delay clk10 high to ldo3 high tp6 36 ns parameter symbol min. max. unit propagation delay clk low to hack high tp1 47 ns propagation delay clk high to cmcs0* low tp2 30 ns propagation delay clk high to cmadr0 high tp3 28 ns propagation delay clk10 high to ldo1 high tp4 51 ns propagation delay clk10 high to ldo2 high tp5 54 ns propagation delay clk10 high to ldo3 high tp6 61 ns
20 7737b?aero?05/08 at7911e 12. ordering information (*) according to atmel quality flow document 4288, see atmel web site. part-number temperature range package quality flow at7911efa-e 25c mqfpl196 engineering sample 5962-08a0101qxc -55c to +125c mqfpl196 mil level b ( *) 5962-08A0101VXC -55c to +125c mqfpl196 space level b (*)
21 7737b?aero?05/08 at7911e 13. package drawings 196 pins ceramic quad flat pack (mqfp_l 196) 14. document revision history 14.1 7737b 1. ordering information updated.
7737b?aero?05/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support aerospace@nto.atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in co nnection with atmel products. no license, express o r implied, by estoppel or otherwise, to any intellectual property right is granted by this docu ment or in connection with the sale of atmel produc ts. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel as sumes no liability whatsoever and disclaims any exp ress, implied or statutory warranty relating to its products including, but no t limited to, the implied warranty of merchantabili ty, fitness for a particular purpose, or non-infringement. in no event shall atm el be liable for any direct, indirect, consequentia l, punitive, special or inciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or los s of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the a ccuracy or completeness of the contents of this doc ument and reserves the right to make changes to spe cifications and product descriptions at any time without notice . atmel does not make any commitment to update the information contained herein. unless specifically p rovided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atm el?s products are not intended, authorized, or warr anted for use as components in applications intended to support o r sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are reg istered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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